//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
//Date        : Tue Nov 12 17:55:51 2019
//Host        : DESKTOP-EVCEGS1 running 64-bit major release  (build 9200)
//Command     : generate_target EDA1_TOP_v3_wrapper.bd
//Design      : EDA1_TOP_v3_wrapper
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module EDA1_TOP_v3_wrapper
   (A0,
    A1,
    A2,
    APM,
    B0,
    B1,
    B2,
    BPM,
    CLK100M,
    DA,
    DB,
    DC,
    DD,
    DE,
    DF,
    DG,
    EN0,
    EN1,
    EN2,
    EN3,
    PMA,
    PMB,
    PMY);
  input A0;
  input A1;
  input A2;
  input APM;
  input B0;
  input B1;
  input B2;
  input BPM;
  input CLK100M;
  output DA;
  output DB;
  output DC;
  output DD;
  output DE;
  output DF;
  output DG;
  output EN0;
  output EN1;
  output EN2;
  output EN3;
  output PMA;
  output PMB;
  output PMY;

  wire A0;
  wire A1;
  wire A2;
  wire APM;
  wire B0;
  wire B1;
  wire B2;
  wire BPM;
  wire CLK100M;
  wire DA;
  wire DB;
  wire DC;
  wire DD;
  wire DE;
  wire DF;
  wire DG;
  wire EN0;
  wire EN1;
  wire EN2;
  wire EN3;
  wire PMA;
  wire PMB;
  wire PMY;

  EDA1_TOP_v3 EDA1_TOP_v3_i
       (.A0(A0),
        .A1(A1),
        .A2(A2),
        .APM(APM),
        .B0(B0),
        .B1(B1),
        .B2(B2),
        .BPM(BPM),
        .CLK100M(CLK100M),
        .DA(DA),
        .DB(DB),
        .DC(DC),
        .DD(DD),
        .DE(DE),
        .DF(DF),
        .DG(DG),
        .EN0(EN0),
        .EN1(EN1),
        .EN2(EN2),
        .EN3(EN3),
        .PMA(PMA),
        .PMB(PMB),
        .PMY(PMY));
endmodule
